This work is concerned with the design of a pseudo-differential Time-to-Amplitude Converter (TAC). The TAC has been developed to achieve low-jitter and low-INL performance and provide two selectable output full-scale ranges (FSRs), namely 100 ns and 1 μs. The pseudo-differential TAC, with a power consumption of 0.26 mW and a total area of 100 x 126 μm2, has been designed in a 65 nm CMOS technology as part of the front-end circuit for the readout of Low Gain Avalanche Diodes (LGADs) based particle detectors for the next generation of space-borne experiments. The paper will present and discuss the proposed TAC architecture and the relevant post-layout simulation results.
Pseudo-Differential Time-to-Amplitude Converter for LGAD Based Particle Detectors
Giroletti S.;Ratti L.;Vacchi C.
2024-01-01
Abstract
This work is concerned with the design of a pseudo-differential Time-to-Amplitude Converter (TAC). The TAC has been developed to achieve low-jitter and low-INL performance and provide two selectable output full-scale ranges (FSRs), namely 100 ns and 1 μs. The pseudo-differential TAC, with a power consumption of 0.26 mW and a total area of 100 x 126 μm2, has been designed in a 65 nm CMOS technology as part of the front-end circuit for the readout of Low Gain Avalanche Diodes (LGADs) based particle detectors for the next generation of space-borne experiments. The paper will present and discuss the proposed TAC architecture and the relevant post-layout simulation results.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
