Cardiovascular Diseases (CVDs) stand as the leading cause of mortality worldwide. Detecting subtle heart sounds alterations in the early stages of CVDs can be crucial for an initial effective treatment. Accordingly, the analysis of Phonocardiograms (PCGs) through segmentation could be helpful for CVDs screening. A well-established algorithm for this task is based on a Convolutional Neural Network (CNN) with an encoding-decoding topology. Prior to the CNN processing., a computationally intensive input pre-processing., based on envelopes extraction, is needed. Thus., achieving real-time performance can be challenging. The main goal of this study is the hardware design., implementation, and evaluation of four PCG pre-processing circuits to be employed together in the design of a low-power point-of-care device for real-time Artificial Intelligence (AI)-based PCG segmentation. Results have shown that the approximations introduced by the fixed-point format and this innovative architecture have a negligible impact on the AI segmentation quality. Finally, the pre-processing chain is real-time compliant., achieving a maximum latency of 257 ms for an available processing window of 1.28 s., while dissipating only 61 mW of power.
FPGA Design of Digital Circuits for Phonocardiogram Pre-Processing Enabling Real-Time and Low-Power AI Processing
Ragusa D.;Gazzoni M.;Torti E.;Marenzi E.;Leporati F.
2024-01-01
Abstract
Cardiovascular Diseases (CVDs) stand as the leading cause of mortality worldwide. Detecting subtle heart sounds alterations in the early stages of CVDs can be crucial for an initial effective treatment. Accordingly, the analysis of Phonocardiograms (PCGs) through segmentation could be helpful for CVDs screening. A well-established algorithm for this task is based on a Convolutional Neural Network (CNN) with an encoding-decoding topology. Prior to the CNN processing., a computationally intensive input pre-processing., based on envelopes extraction, is needed. Thus., achieving real-time performance can be challenging. The main goal of this study is the hardware design., implementation, and evaluation of four PCG pre-processing circuits to be employed together in the design of a low-power point-of-care device for real-time Artificial Intelligence (AI)-based PCG segmentation. Results have shown that the approximations introduced by the fixed-point format and this innovative architecture have a negligible impact on the AI segmentation quality. Finally, the pre-processing chain is real-time compliant., achieving a maximum latency of 257 ms for an available processing window of 1.28 s., while dissipating only 61 mW of power.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.