A 55-fJ/Comparison Dynamic Current Comparator with Parasitic Charge Recycling Technique

This paper introduces a dynamic current comparator employing a parasitic charge recycling technique to achieve an ultra-low energy per comparison of 175 fJ. Furthermore, incorporating a switched capacitor supply in the static portion of the circuit, the comparison energy is further reduced to 55 fJ, more than three times lower. The proposed circuit, designed and extensively simulated in a 130-nm CMOS process with thick gate MOS transistors, demonstrates a comparison time of 3.8 ns, with a 100-nA input difference and a 32-MHz clock, while offering an input-referred noise of 2.9 nArms. These features make the proposed comparator highly suitable for medium-to high-resolution data conversion systems, particularly in biomedical and sensor-readout applications. Additionally, it is well-suited for high-speed and cryogenic CMOS systems, where current-mode architectures are becoming increasingly relevant.