This paper introduces a quasi-passive Noise-Shaping Successive Approximation Register Analog-to-Digital converter (NS-SAR ADC) suited for low power Audio Activity Detection (AAD). Exploiting a 2nd order Error-Feedback (EF) loop filter implemented through a low power open loop amplifier, insensitive to Process-Voltage-Temperature (PVT) variations, and a fully passive Charge-Sharing (CS) summing node, this converter reaches 78 dB of Dynamic Range (DR), achieving a Schreier Figure-of-Merit (FoMs) of 165.3 dB. Fabricated in a 65-nm BCD process, the proposed ADC core occupies 0.129 μm2 consuming 14.9 μW from a 1.2-V supply.
A 14.9-µW Quasi-Passive Error-Feedback Noise-Shaping SAR Converter with 78-dB Dynamic Range for Audio Activity Detection
Tambussi, Marco;Grassi, Marco;Bonizzoni, Edoardo;Malcovati, Piero
2025-01-01
Abstract
This paper introduces a quasi-passive Noise-Shaping Successive Approximation Register Analog-to-Digital converter (NS-SAR ADC) suited for low power Audio Activity Detection (AAD). Exploiting a 2nd order Error-Feedback (EF) loop filter implemented through a low power open loop amplifier, insensitive to Process-Voltage-Temperature (PVT) variations, and a fully passive Charge-Sharing (CS) summing node, this converter reaches 78 dB of Dynamic Range (DR), achieving a Schreier Figure-of-Merit (FoMs) of 165.3 dB. Fabricated in a 65-nm BCD process, the proposed ADC core occupies 0.129 μm2 consuming 14.9 μW from a 1.2-V supply.File in questo prodotto:
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