This paper investigates the impact of the input resistor thermal noise in high-resolution hybrid continuous-time/discrete-time (CT-DT) Σ Δ analog-to-digital converters (ADCs), with particular emphasis on the co-design of the input buffer and the ADC front-end. Targeting Industry 4.0 sensor interface applications, where accuracy and power efficiency are critical, this work addresses how the thermal noise originating in the CT stage limits the system signal-to-noise-ratio (SNR). A modeling strategy for this noise contribution is introduced and validated through Simulink® simulations, using a colored-noise approach, enabling a realistic spectral representation and accurate performance prediction. The proposed architecture, a thirdorder hybrid cascade-of-integrators-with-feedforward (CIFF) Σ Δ modulator, demonstrates compelling trade-offs between resolution, power consumption, and area. The adopted design choices are guided by analytical insights into integrator gain, RC time constants, and their effect on SNR performance. Simulation results confirm the effectiveness of the proposed approach, showcasing a 111.7-dB SNR with a 0.8-V input signal, at a 10.24-MHz sampling frequency.
Analysis of the Input Resistor Thermal Noise in High Precision Hybrid CT-DT ΣΔ ADCs
Di Francesco L.
;Aprile A.;Moisello E.;Bonizzoni E.;Malcovati P.
2025-01-01
Abstract
This paper investigates the impact of the input resistor thermal noise in high-resolution hybrid continuous-time/discrete-time (CT-DT) Σ Δ analog-to-digital converters (ADCs), with particular emphasis on the co-design of the input buffer and the ADC front-end. Targeting Industry 4.0 sensor interface applications, where accuracy and power efficiency are critical, this work addresses how the thermal noise originating in the CT stage limits the system signal-to-noise-ratio (SNR). A modeling strategy for this noise contribution is introduced and validated through Simulink® simulations, using a colored-noise approach, enabling a realistic spectral representation and accurate performance prediction. The proposed architecture, a thirdorder hybrid cascade-of-integrators-with-feedforward (CIFF) Σ Δ modulator, demonstrates compelling trade-offs between resolution, power consumption, and area. The adopted design choices are guided by analytical insights into integrator gain, RC time constants, and their effect on SNR performance. Simulation results confirm the effectiveness of the proposed approach, showcasing a 111.7-dB SNR with a 0.8-V input signal, at a 10.24-MHz sampling frequency.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
