Voltage monitoring circuits are a fundamental block in energy-harvesting-powered applications, as typically the system operation has to be enabled only after a certain supply voltage is reached after a cold start or intermediate voltage levels have to be detected during start-up. The voltage values of interest vary depending on the specific system; hence, a versatile voltage monitoring circuit scheme that can be easily adapted for the desired voltage is particularly appealing. Furthermore, in energy-harvesting-powered applications, special care must be paid to power consumption minimization, in order to ensure self-sustainability of the system, and to area occupation, thus enabling a small form factor and low cost. To address these requirements, this paper proposes a novel, highly versatile voltage-monitoring circuit for energy-harvesting-powered applications that minimizes power consumption and area occupation. Indeed, the proposed voltage monitor implementation, relying on cascaded PMOS-based and NMOS-based voltage detectors, can be easily adapted to any desired voltage level, also achieving high voltage levels to be detected by adding (multiple) diode-connected transistors in the first stage while maintaining the voltage monitor output rail-to-rail and avoiding static power consumption from the cascaded digital gates. The proposed solution, targeting a 800 mV voltage level to be detected, was designed in a 180 nm CMOS triple-well technology and extensively validated through simulations in Cadence Virtuoso. Furthermore, it was bench-marked with an implementation in the same process based on the standard voltage monitor scheme (including the necessary cascaded logic gates for achieving a rail-to-rail output) available in literature, showcasing a reduction up to about 1700× in power consumption and 3.87× in area occupation, considering a preliminary area estimation, when triple-well devices are employed, whereas, when relying only on standard devices, although no significat area benefit is obtained, a reduction of up to about 400× in power consumption is achieved.
A Novel and Highly Versatile Voltage Monitoring Circuit Enabling Power Consumption and Area Minimization
Moisello, Elisabetta
;Cabrini, Alessandro;Bonizzoni, Edoardo;Malcovati, Piero
2026-01-01
Abstract
Voltage monitoring circuits are a fundamental block in energy-harvesting-powered applications, as typically the system operation has to be enabled only after a certain supply voltage is reached after a cold start or intermediate voltage levels have to be detected during start-up. The voltage values of interest vary depending on the specific system; hence, a versatile voltage monitoring circuit scheme that can be easily adapted for the desired voltage is particularly appealing. Furthermore, in energy-harvesting-powered applications, special care must be paid to power consumption minimization, in order to ensure self-sustainability of the system, and to area occupation, thus enabling a small form factor and low cost. To address these requirements, this paper proposes a novel, highly versatile voltage-monitoring circuit for energy-harvesting-powered applications that minimizes power consumption and area occupation. Indeed, the proposed voltage monitor implementation, relying on cascaded PMOS-based and NMOS-based voltage detectors, can be easily adapted to any desired voltage level, also achieving high voltage levels to be detected by adding (multiple) diode-connected transistors in the first stage while maintaining the voltage monitor output rail-to-rail and avoiding static power consumption from the cascaded digital gates. The proposed solution, targeting a 800 mV voltage level to be detected, was designed in a 180 nm CMOS triple-well technology and extensively validated through simulations in Cadence Virtuoso. Furthermore, it was bench-marked with an implementation in the same process based on the standard voltage monitor scheme (including the necessary cascaded logic gates for achieving a rail-to-rail output) available in literature, showcasing a reduction up to about 1700× in power consumption and 3.87× in area occupation, considering a preliminary area estimation, when triple-well devices are employed, whereas, when relying only on standard devices, although no significat area benefit is obtained, a reduction of up to about 400× in power consumption is achieved.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
