A 7-bit ECL-Based DTC with Improved INL

This paper presents a 7-bit digital-to-time converter (DTC) architecture based on emitter-coupled logic (ECL), designed for noise-critical and radiation-hardened applications where low-volume components are required and CMOS technologies may prove inadequate. The proposed DTC employs a variable-slope delay mechanism utilizing a digitally controlled capacitor array, achieving a resolution of 530 femtoseconds (fs) and a delay range of 67.3 picoseconds (ps). To enable the generation of clean square-wave outputs, two recovery stage topologies are analyzed. A modified ECL recovery stage, incorporating cross-coupled negative capacitance, is proposed to address the trade-off between phase noise and integral nonlinearity (INL). Simulation results indicate that the modified design achieves a systematic peak INL of 20 fs, representing a significant improvement over CMOS counterparts. The phase noise floor reaches -160.8 dBc/Hz, with a 4 0 0 - H z flicker noise corner frequency at a 200-MHz input signal, offering competitive noise performance. These benefits are realized at the cost of an increased power consumption of 24 mW.