Optimizing the Energy Efficiency in SAR ADCs with Linear/Exponential Comparator Biasing

This paper presents comparator biasing techniques for energy-efficient optimization in successive-approximation-register (SAR) analog-to-digital converters (ADCs). The proposed approaches leverage the non-uniform decision complexity across SAR conversion cycles by employing a biasing-pattern register (BPR) to dynamically adjust the bias current of the comparator preamplifier through a current-mode digital-to-analog converter (IDAC). Four BPR-driven biasing profiles - namely dual-mode, linear, exponential, and hybrid are introduced and evaluated against the conventional uniform one. Simulations and analysis of an 8-bit SAR ADC demonstrate that the hybrid biasing scheme achieves approximately a 67% improvement in the normalized Walden figure of merit (FoMWN) compared to the static biasing scheme. Notably, this implies that the improvement in-terms of power reduction is achieved with sub 1 dB degradation in signal-to-noise-and-distortion ratio (SNDR).