This paper presents a 6.4-GS/s digital-to-analog converter (DAC) designed for D-band backhaul transmitters employing digital pre-distortion (DPD). A comprehensive noise analysis to optimize the DAC performance within the noise-power trade-off is proposed; in addition, optimal segmentation selection is discussed to address dynamic linearity under area and digital complexity constraints. The DAC was fabricated in a 55-nm BiCMOS process, and both experimental and post-layout Monte Carlo results are presented. With a 10-bit resolution, it achieves a -163.7-dBm/Hz noise spectral density (NSD), measured at 1 GHz. The DAC SFDR is >51.2 dBc, while its IM3 is <-60.6 dBc. With a state-of-the-art 22-mW total power consumption, the proposed DAC achieves a remarkable figure-of-merit (FoM) of 194 PHz/W.
A 10-bit 6.4-GS/s Current Steering DAC with -163.7 dBm/Hz Noise Spectral Density for DPD-Based D-Band Backhaul Transmitters
Aprile A.
;Bonizzoni E.;Malcovati P.
2026-01-01
Abstract
This paper presents a 6.4-GS/s digital-to-analog converter (DAC) designed for D-band backhaul transmitters employing digital pre-distortion (DPD). A comprehensive noise analysis to optimize the DAC performance within the noise-power trade-off is proposed; in addition, optimal segmentation selection is discussed to address dynamic linearity under area and digital complexity constraints. The DAC was fabricated in a 55-nm BiCMOS process, and both experimental and post-layout Monte Carlo results are presented. With a 10-bit resolution, it achieves a -163.7-dBm/Hz noise spectral density (NSD), measured at 1 GHz. The DAC SFDR is >51.2 dBc, while its IM3 is <-60.6 dBc. With a state-of-the-art 22-mW total power consumption, the proposed DAC achieves a remarkable figure-of-merit (FoM) of 194 PHz/W.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
