Linearization Technique for CCO-Based ADCs for AiMC MVM Architectures Using Resistive Memory Devices

This brief presents a design technique to linearize the frequency-to-conductance characteristic of a Current- Controlled Oscillator (CCO) within a CCO-based ADC used for Matrix-Vector Multiplication (MVM) in Analog in-Memory Computing (AiMC) accelerators. The proposed linearization is achieved by leveraging a bitline voltage regulator (BLVR), a circuit commonly employed to bias the bitlines (BLs) of computational resistive memory arrays. The BLVR utilizes a resistor and a copy of the bitline current to create a feedback mechanism that dynamically adjusts the bitline voltage in response to changes in the total bitline conductance (gBL). This feedback reduces the oscillation period by an amount that linearizes the relationship between the CCO output frequency ( fCCO) and gBL. Simulations in 28 nm FD-SOI technology demonstrate that the proposed BLVR reduces the quadratic coefficient k2 of a polynomial approximation of the fCCO-gBL characteristic from 5:88 × 10-2 to 2:31 × 10-2, corresponding to a 2:5× improvement in linearity in the full conductance range.