VDSL2 transceivers use a wide analog bandwidth to achieve bit-rates in excess of 200 Mb/s. For standard 6-band VDSL2, 30 MHz bandwidth is required, comprising three up-stream and three down-stream signals. Since discrete multi tone (DMT) modulation is used, distortion components for the signal chain have to be below -65dBc to fully exploit 15b-per-tone bit loading. The presented AFE is implemented in a 0.15 mum triple-oxide CMOS process and uses three voltage supplies: 1.0 V for digital, 3.3 V for analog, and 7 V for the on-chip line driver (LD). All transceiver functionality is included in a single chip. The dynamic-range requirement of the receiver is achieved by the combination of a 2-stage 39 dB programmable-gain amplifier/anti-aliasing filter (PGA) followed by a 14b pipelined ADC, plus an analog echo canceller made of a 14b DAC followed by an adjustable-gain amplifier/filter.
A VDSL2 CPE AFE in 0.15µm CMOS with integrated line driver
CASTELLO, RINALDO;
2009-01-01
Abstract
VDSL2 transceivers use a wide analog bandwidth to achieve bit-rates in excess of 200 Mb/s. For standard 6-band VDSL2, 30 MHz bandwidth is required, comprising three up-stream and three down-stream signals. Since discrete multi tone (DMT) modulation is used, distortion components for the signal chain have to be below -65dBc to fully exploit 15b-per-tone bit loading. The presented AFE is implemented in a 0.15 mum triple-oxide CMOS process and uses three voltage supplies: 1.0 V for digital, 3.3 V for analog, and 7 V for the on-chip line driver (LD). All transceiver functionality is included in a single chip. The dynamic-range requirement of the receiver is achieved by the combination of a 2-stage 39 dB programmable-gain amplifier/anti-aliasing filter (PGA) followed by a 14b pipelined ADC, plus an analog echo canceller made of a 14b DAC followed by an adjustable-gain amplifier/filter.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
