A 3 GHz six phases PLL clock synthesizer embedded in a complete Serial Advanced Technology Attachment (SATA) standard compliant oversampling PHY is presented. Multiphase frequency synthesis has been realized using an LC ring structure VCO, featuring improved phase noise and phase accuracy. Integrated in a standard 0.13 /spl mu/m CMOS process the synthesizer has an active area of 0.8 mm/sup 2/ and consumes 35 mW while achieving a phase noise of -120dBc/Hz @ 1MHz and a maximum measured phase error of 0.3/spl deg/. In addition a novel analytical method to investigate the phase accuracy properties of LC ring structures is presented and validated through simulations.
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