A 2/sup nd/-order 4b /spl Delta//spl Sigma/ modulator in cascade with a 9b pipeline clocked at 80MHz achieves 75dB DR, 74dB peak SNR and more than 87dB SFDR in a 10MHz bandwidth by means of background digital linearization and noise-cancellation algorithms. The 0.18/spl mu/m CMOS chip consumes 240mW including reference generator, digital decimator and correction logic
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Titolo: | An 80MHz 4/spl times/ oversampled cascaded/spl Delta/spl Sigma/-pipelined ADC with 75dB DR and 87dB SFDR | |
Autori: | ||
Data di pubblicazione: | 2005 | |
Abstract: | A 2/sup nd/-order 4b /spl Delta//spl Sigma/ modulator in cascade with a 9b pipeline clocked at 80MHz achieves 75dB DR, 74dB peak SNR and more than 87dB SFDR in a 10MHz bandwidth by means of background digital linearization and noise-cancellation algorithms. The 0.18/spl mu/m CMOS chip consumes 240mW including reference generator, digital decimator and correction logic | |
Handle: | http://hdl.handle.net/11571/23891 | |
ISBN: | 9780780389045 | |
Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
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