A CMOS receiver able to correctly answer to the standard IEEE 1596-1992 Scalable Coherent Interface specifications is proposed. The receiver recognises and translates into CMOS digital levels a differential signal of amplitude down to 100 mV and frequency up to 1 GHz and, with 2.5V of voltage supply, exhibits a power dissipation always lower than 11.5mW and a duty-cycle output always between 45% and 55%, independently on the input common mode value. The circuit has been designed in CMOS technology, 0.25um minimum litography.
A receiver for standard IEEE 1596-1992 scalable coherent interface
FEDELI, MICHELE;VACCHI, CARLA
1999-01-01
Abstract
A CMOS receiver able to correctly answer to the standard IEEE 1596-1992 Scalable Coherent Interface specifications is proposed. The receiver recognises and translates into CMOS digital levels a differential signal of amplitude down to 100 mV and frequency up to 1 GHz and, with 2.5V of voltage supply, exhibits a power dissipation always lower than 11.5mW and a duty-cycle output always between 45% and 55%, independently on the input common mode value. The circuit has been designed in CMOS technology, 0.25um minimum litography.File in questo prodotto:
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