A chip for image processing called SCPC1 (silicon compiler pyramidal chip) is presented. It belongs to the image-processing-dedicated ASIC family and can be used to build massively parallel, hierarchical systems to perform image processing at different levels of resolution. The purpose of this project is twofold: testing the facilities offered by the design tool (a silicon compiler) when managing nonconventional, bit-serial architectures and obtaining a modular, extendible chip architecture that allows for increased integration of PEs in a single chip

SCPC1: silicon compiler pyramidal chip

ALBANESI, MARIA GRAZIA;FERRETTI, MARCO
1989

Abstract

A chip for image processing called SCPC1 (silicon compiler pyramidal chip) is presented. It belongs to the image-processing-dedicated ASIC family and can be used to build massively parallel, hierarchical systems to perform image processing at different levels of resolution. The purpose of this project is twofold: testing the facilities offered by the design tool (a silicon compiler) when managing nonconventional, bit-serial architectures and obtaining a modular, extendible chip architecture that allows for increased integration of PEs in a single chip
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11571/461442
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