The low quality factor of passive components at mm-wave limits the impedance magnitude of resonators and leads to poor current to voltage conversion in amplifiers. To achieve significant LNA gain at mm-wave, multiple stages are required with the consequence of large power dissipation. Delaying the current to voltage conversion at intermediate frequency while processing the mm-wave signal in current domain is pursued in this work. LNA and mixer are merged in a single stage and show an overall front-end noise figure comparable to state of the art CMOS stand-alone LNAs. In view of integration of large phased arrays for wireless data transfers at Gbit/s, the solution offers the key advantage of an extremely low power consumption together with a very low occupied area. Test chips realized in 65nm CMOS, show the following performances: 48GHz to 62GHz input frequency range, conversion gain of 17dB and minimum noise figure of 6.5dB when translating the signal to an intermediate frequency of 18.5GHz. Power dissipation and die area are 5mW and 320 x 170 m2 only. Normalizing performances by means of the usually adopted figure of merit for LNAs, the proposed front-end outperforms all recently published CMOS LNAs while providing both amplification and frequency translation.

A 5mW CMOS wideband mm-wave front-end featuring 17dB of conversion gain and 6.5 dB minimum NF

GHILIONI, ANDREA;MAZZANTI, ANDREA
2012-01-01

Abstract

The low quality factor of passive components at mm-wave limits the impedance magnitude of resonators and leads to poor current to voltage conversion in amplifiers. To achieve significant LNA gain at mm-wave, multiple stages are required with the consequence of large power dissipation. Delaying the current to voltage conversion at intermediate frequency while processing the mm-wave signal in current domain is pursued in this work. LNA and mixer are merged in a single stage and show an overall front-end noise figure comparable to state of the art CMOS stand-alone LNAs. In view of integration of large phased arrays for wireless data transfers at Gbit/s, the solution offers the key advantage of an extremely low power consumption together with a very low occupied area. Test chips realized in 65nm CMOS, show the following performances: 48GHz to 62GHz input frequency range, conversion gain of 17dB and minimum noise figure of 6.5dB when translating the signal to an intermediate frequency of 18.5GHz. Power dissipation and die area are 5mW and 320 x 170 m2 only. Normalizing performances by means of the usually adopted figure of merit for LNAs, the proposed front-end outperforms all recently published CMOS LNAs while providing both amplification and frequency translation.
2012
9781467304139
9781467304153
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11571/567875
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