Ultra Low-Power, Area-Efficient Multiplier Based on Shift-and-Add Architecture

SUB-and-add multipliers have a simpler structure than other types of multipliers and, at the same time, have a lower operating speed. They are suitable for applications where speed is not the first design priority. In this paper, we present a low-power, low-area multiplier with a simplest possible structure based on shift-and-add which can be a good choice for portable applications and medical devices such as a pacemaker, where power reduction and chip area are core issues. The main idea of the article is to use multiplexers and appropriate timing signals. By applying these signals to the multiplexer selection lines, it is possible to achieve the correct output with an n-bit adder and input-output registers during (2n+1) clock pulse. Simulation results of proposed 16*16-bit multiplier using HSPICE in standard 0.18um CMOS technology demonstrate that it has 129ns propagation delay while the corresponding power consumption is 467 mu W.