This paper presents a capacitive level-shifter circuit for a 100-V monolithic 1-μm GaN-on-Si half bridge, designed to achieve the lowest and most thermally stable response time possible. The circuit employs a novel active pull-up that uses depletion transistors connected with the source to the upper supply to achieve a faster output latch commutation. The proposed design achieves rise and fall delays of 2.29 ns and 2.14 ns, respectively, with a temperature stability of 1.28 ps/°C. It can switch at 5 MHz, withstand switching node noise up to 500 V/ns, and transmit signals with the switching node at -100 V, all within an area of only 0.14 mm2.
A 2.3-ns Response Time Temperature Insensitive Capacitive Level-Shifter with a Novel Active Pull-up for a 100-V Monolithic GaN Half Bridge
Tardani T. F.
;Aprile A.;Moisello E.;Bonizzoni E.;Malcovati P.
2026-01-01
Abstract
This paper presents a capacitive level-shifter circuit for a 100-V monolithic 1-μm GaN-on-Si half bridge, designed to achieve the lowest and most thermally stable response time possible. The circuit employs a novel active pull-up that uses depletion transistors connected with the source to the upper supply to achieve a faster output latch commutation. The proposed design achieves rise and fall delays of 2.29 ns and 2.14 ns, respectively, with a temperature stability of 1.28 ps/°C. It can switch at 5 MHz, withstand switching node noise up to 500 V/ns, and transmit signals with the switching node at -100 V, all within an area of only 0.14 mm2.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
