CASTELLO, RINALDO

CASTELLO, RINALDO  

DIPARTIMENTO DI INGEGNERIA INDUSTRIALE E DELL'INFORMAZIONE  

Mostra records
Risultati 1 - 20 di 230 (tempo di esecuzione: 0.088 secondi).
Titolo Data di pubblicazione Autore(i) File
"100 V High Performance Amplifiers in BCD Technology for SLIC Applications," 1-gen-1990 Castello, Rinaldo; Lari, F.; Siligoni, M.; Tomasini, L.
"A 2G/3G Cellular Analog Baseband Based on a Filtering ADC" 1-gen-2012 Sosio, M.; Liscidini, Antonio; Castello, Rinaldo
"A 36mW/9mW power-scalable DCO in 55nm CMOS for GSM/WCDMA frequency synthesizers" 1-gen-2012 Liscidini, A.; Fanori, L.; Andreani, P.; Castello, Rinaldo
"A Dither-Less All Digital PLL for Cellular Transmitters," 1-gen-2012 Vercesi, Luca; Fanori, L.; De Bernardinis, F.; Liscidini, Antonio; Castello, Rinaldo
"A Floating CMOS Bandgap Voltage Reference For Differential Applications" 1-gen-1988 Ferro, M; Salerno, F.; Castello, Rinaldo
"A Low-Voltage High-Drive Differential Amplifier For ISDN Applications," 1-gen-1988 Tomasini, L.; Gola, A.; Castello, Rinaldo
"A very linear BiCMOS transconductor for high-frequency filtering applications," 1-gen-1990 Castello, Rinaldo; Montecchi, Federico; Alini, R.; Baschirotto, Andrea
"Finite gain compensation techniques for high-Q bandpass SC filters," 1-gen-1990 Baschirotto, Andrea; Castello, Rinaldo; Montecchi, Federico
"IC Thermal Modeling" 1-gen-1977 Castello, Rinaldo; Antognetti, P.
1.5-V high-performance SC filters in BiCMOS technology 1-gen-1991 Castello, Rinaldo; L., Tomasini
100-V high performance amplifiers in BCD technology for slic applications 1-gen-1992 Castello, Rinaldo; M., Siligoni; L., Tomasini
1V Switched-capacitor filters 1-gen-1999 Baschirotto, Andrea; Castello, Rinaldo
3.3GHz DCO with a frequency resolution of 150Hz for All-digital PLL 1-gen-2010 Fanori, Luca; Liscidini, Antonio; Castello, Rinaldo
72-mW CMOS 802.11a direct conversion front-end with 3.5-dB NF and 200-kHz 1/f noise corner 1-gen-2005 Mario, Valla; Giampiero, Montagna; Castello, Rinaldo; Riccardo, Tonietto; Ivan, Bietti
A +25 dBm IIP3 1.7-2.1 GHz FDD Receiver Front-End with Integrated Hybrid-Transformer in 28nm CMOS 1-gen-2017 Fabiano, Ivan; Ramella, Matteo; Manstretta, Danilo; Castello, Rinaldo
A 0.08mm21-6.2 GHz Receiver Front-End with Inverter-Based Shunt-Feedback Balun-LNA 1-gen-2020 Guo, B.; Prevedelli, D.; Castello, R.; Manstretta, D.
A 0.13/spl mu/m CMOS front-end for DCS1800/UMTS/802.11b-g with multi-band positive feedback low noise amplifier. 1-gen-2005 Liscidini, Antonio; M., Brandolini; D., Sanzogni; Castello, Rinaldo
A 0.13/spl mu/m CMOS front-end, for DCS1800/UMTS/802.11b-g with multiband positive feedback low-noise amplifier. 1-gen-2006 Liscidini, Antonio; Brandolini, Massimo; Sanzogni, Davide; Castello, Rinaldo
A 0.18 µm CMOS TIA plus Limiting Amplifier for 8 Gb/s Fiber Optic Communications 1-gen-2003 M., Pisati; F., Gatta; Castello, Rinaldo; Svelto, Francesco; C., Bazzani
A 0.18 μm CMOS direct-conversion receiver front-end for UMTS 1-gen-2002 Manstretta, Danilo; Castello, Rinaldo; F., Gatta; P., Rossi; Svelto, Francesco