IRIS
CABRINI, ALESSANDRO
 Distribuzione geografica
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Continente #
NA - Nord America 2.706
EU - Europa 2.143
AS - Asia 1.320
AF - Africa 5
OC - Oceania 5
SA - Sud America 4
Totale 6.183
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Nazione #
US - Stati Uniti d'America 2.694
CN - Cina 1.288
IE - Irlanda 798
UA - Ucraina 346
FI - Finlandia 224
DE - Germania 218
IT - Italia 198
SE - Svezia 147
GB - Regno Unito 113
BE - Belgio 37
FR - Francia 35
IN - India 15
CA - Canada 12
NL - Olanda 6
RU - Federazione Russa 6
AU - Australia 4
BR - Brasile 4
ES - Italia 4
HK - Hong Kong 4
IR - Iran 4
MU - Mauritius 4
RO - Romania 4
TW - Taiwan 3
CH - Svizzera 2
MY - Malesia 2
PL - Polonia 2
AM - Armenia 1
AT - Austria 1
DZ - Algeria 1
GR - Grecia 1
KR - Corea 1
LV - Lettonia 1
NZ - Nuova Zelanda 1
SA - Arabia Saudita 1
TR - Turchia 1
Totale 6.183
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Città #
Dublin 796
Chandler 700
Jacksonville 457
Nanjing 361
Nanchang 173
Ann Arbor 156
Ashburn 153
Beijing 144
Shenyang 118
Princeton 117
Lawrence 112
Medford 104
Wilmington 97
Hebei 95
Changsha 93
Jiaxing 88
Hangzhou 61
Boardman 58
Tianjin 55
Milan 46
Woodbridge 43
Helsinki 37
Pavia 37
Brussels 35
Shanghai 26
Des Moines 22
Norwalk 22
Verona 18
Duncan 14
Seattle 14
Fairfield 13
Pune 13
Kunming 10
New York 10
Redwood City 10
Toronto 10
Jinan 8
Ningbo 8
West Jordan 8
Zhengzhou 8
Dearborn 7
Houston 7
Los Angeles 7
Somma Lombardo 7
Washington 7
Taizhou 6
Guangzhou 5
Hanover 5
Cardano 4
Lanzhou 4
Neubiberg 4
Orange 4
Alba 3
Auburn Hills 3
Banqiao 3
Barcelona 3
Bucharest 3
Florence 3
Menlo Park 3
Monmouth Junction 3
Padova 3
Aachen 2
Abbiategrasso 2
Ardabil 2
Castano Primo 2
Cedar Knolls 2
Chicago 2
Hefei 2
Lomazzo 2
London 2
Marseille 2
Melbourne 2
Piemonte 2
Redmond 2
Rome 2
Rovellasca 2
São Paulo 2
Vigasio 2
Walnut 2
Acqui Terme 1
Augusta 1
Berlin 1
Biella 1
Bloomfield 1
Borås 1
Calgary 1
Changchun 1
Chennai 1
Constanța 1
Cwmbran 1
Geislingen an der Steige 1
Gothenburg 1
Groningen 1
Guiyang 1
Haikou 1
Halle 1
Kraków 1
Las Vegas 1
Lausanne 1
Mansfield 1
Totale 4.501
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Nome #
A 0.13-µm CMOS NOR Flash memory experimental chip for 4-b/cell digital storage 139
A 1 V, 26 µW extended temperature range band-gap reference in 130-nm CMOS technology 107
A 1.2 V sense amplifier for high-performance embeddable NOR Flash memories 92
High-efficiency CMOS charge pump 82
A theoretical discussion on performance limits of CMOS charge pumps 81
On-wafer integrated system for fast characterization and parametric test of new-generation Non Volatile Memories 80
Design of maximum-efficiency integrated voltage doubler 79
CMOS discrete-time chaotic circuit for low-power embedded cryptosystems 78
On the effect of cell geometry on the amorphization process in phase-change memories 78
Effects of alloy composition on multilevel operation in self-heating Phase Change Memories 77
Data retention of partial-SET states in phase change memories 76
Impact of parasitic elements on CMOS charge pumps: a numerical analysis 75
Cancellation of Amplifier Offset and 1/f Noise: An Improved Chopper Stabilized Technique 75
Modeling of partial-RESET dynamics in Phase Change Memories 75
Theoretical analysis of the RESET operation in phase-change memories 74
A charge transfer scheme for efficiency optimization in integrated charge pumps 74
Method for multilevel programming of phase change memory cells using adaptive reset pulses 73
On-wafer analog pulse generator for fast characterization and parametric test of resistive switching memories 73
A discussion on exponential gain charge pump 72
A Very Fast and Low-power Time-discrete Spread-spectrum Signal Generator 71
A novel programming technique to boost low-resistance state performance in Ge-rich GST Phase Change Memory 71
A 32-KB ePCM for real-time data processing in automotive and smart power applications 71
Voltage-driven multilevel programming in phase change memories 70
A compact low-cost test equipment for thermal and electrical characterization of integrated circuits 69
Efficiency comparison between doubler and Dickson charge pumps 68
Temperature dependence of the programmed states in GST-based multilevel phase-change memories 68
Algorithm for automatic design of maximum-efficiency Dickson charge pumps 68
A small-size, fast-settling, low-cost thermal regulator for chip surface measurements 67
A test chip for contact and via failure analysis for 90-nm copper interconnect CMOS technology 67
Theoretical and experimental analysis of Dickson charge pump output resistance 66
Effect of technology scaling on program and read window in phase change memories 66
A versatile and compact USB system for electrical and thermal characterization of non-volatile memories 65
Sound representation in higher language areas during language generation. 65
Thermal regulator for IC temperature characterization using a microprobe station 64
A bipolar-selected phase-change memory featuring multi-level cell storage 64
Impact of control signal non-idealities on two-phase charge pumps 63
Improved charge pump for Flash memory applications in triple-well CMOS technology 63
Use of the non-linear Chua's circuit for on-line offset calibration of ADC 62
Programming a multilevel phase change memory cell 62
Enhanced charge pump for ultra-low-voltage applications 62
A circuit for linearly decreasing temperature SET programming of PCM based on Ge-rich GST 62
Impact of control signal skews on self-boosted charge pumps 61
Low-field resistance drift in partial-SET states in Phase Change Memories 61
High-swing buffer for programmable resistive memories 61
High-accuracy program scheme for multilevel Flash memories 60
Statistical modeling of bit distributions in phase change memories 60
Temperature tracking current reference for multilevel phase-change memories 60
Voltage gain analysis of integrated Fibonacci-like charge pumps for low-power applications 60
High input range sense comparator for multilevel Flash memories 60
Transient effects in partial-RESET programming of phase change memory cells 59
A failure analysis test structure for deep sub-micron CMOS copper interconnect technologies 58
On-Line Calibration of Offset and Gain Mismatch in Time-Interleaved ADC Using a Sampled-Data Chaotic Bit-Stream 58
On voltage-driven multilevel programming in phase change memory cells 58
Challenges and opportunities for information theory-based design of Phase Change Memories 58
Experimental analysis of partial-SET state stability in phase change memories 58
Power efficiency evaluation in Dickson and voltage doubler charge pump topologies 57
Current pulse generator for multilevel cell programming of innovative PCM 57
A theoretical charge transfer scheme for efficiency optimization of integrated charge pumps 56
A 32KB 18ns random access time embedded PCM with enhanced program throughput for automotive and smart power applications 56
High-efficiency regulator for on-chip charge pump voltage elevators 55
Trade-off between SET and data retention performance thanks to innovative materials for Phase-Change Memory 55
A charge pump with enhanced charge transfer for energy harvesting applications 55
An integrated multi-physics approach to the modeling of a phase-change memory device 54
Impact of technology scaling of phase-change memory performance 54
Current reference scheme for multilevel Phase-Change Memory sensing 54
Dependence of resistance drift on the amorphous cap size in phase change memory arrays 53
Experimental evaluation of a low-power sense comparator for multilevel Flash memories 53
A test structure for contact and via failure analysis in deep-submicrometer CMOS technologies 53
Drift-driven investigation of phase distribution in Phase-Change Memories 53
Analysis of array biasing in crosspoint memories for leakage power minimization 53
Method for designing integrated charge pumps with minimum area 52
Feasibility study of partial-RESET multilevel programming in Phase Change Memories 52
Novel test strategy for statistical evaluation of defect density and reliability of contacts and vias 52
Temperature study of high-drive capability buffer for Phase Change Memories 52
Compact model for phase change memory cells 52
Voltage-mode closed-loop sense amplifier for multilevel Flash memories 50
High-efficiency control structure for CMOS Flash memory charge pumps 50
Development and Analysis of a PCB Vector 2-D Magnetic Field Sensor System for Electronic Compasses 49
Single-ended phase-change memory device and reading method 49
SET Performance Improvement in Phase Change Memory Based on Innovative materials Featuring High Temperature Data Retention 48
Algorithms to survive: programming operation in non-volatile memories 48
System and method for a multistage operational amplifier 48
Optimal programming with voltage-controlled temperature profile to reduce SET state distribution dispersion in PCM 48
Intrinsic program instability in HfO2 RRAM and consequences on program algorithms 47
A comprehensive Verilog-A behavioral model of Spin-Transfer Torque memory cell 47
Automatic trimming procedure to enhance the accuracy of on-chip analog pulse generators 47
Optimized temperature profile based pulse generator for innovative Phase Change Memory 47
A variability-aware analysis and design guideline for write and read operations in crosspoint STT-MRAM arrays 46
Leakage-resilient memory-based physical unclonable function using phase change material 45
High-drive capability buffer for highly variable resistive loads 44
Enhanced voltage buffer compensation technique for two-stage CMOS operational amplifiers 44
Voltage-driven partial-RESET multilevel programming in phase-change memories 44
Program and read scaling trade-offs in phase change memories 43
Exploiting process variations and programming sensitivity of Phase Change Memory for reconfigurable physical unclonable functions 43
On-chip error correcting techniques for new-generation flash memories 43
Tracking of the speech envelope by neural activity during speech production is not limited to Broca's area in the dominant frontal lobe 42
2-Mb embedded phase change memory with 16-ns read access time and 5-Mb/s write throughput in 90-nm BCD technology for automotive applications 42
Optimization of low-resistance state performance in Ge-rich GST Phase Change Memory 41
Magnetic field analysis for the optimization of a GMR isolator for data transmission in power applications 40
Bandwidth optimization of CMOS two-stage operational amplifiers under power consumption and area constraints 39
Totale 6.058
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Categoria #
all - tutte 20.828
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 20.828
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2018/201928 0 0 0 0 0 0 0 0 0 14 4 10
2019/20201.535 415 645 0 68 6 64 27 76 4 121 106 3
2020/2021692 96 58 15 74 6 80 15 117 29 103 81 18
2021/2022577 4 7 19 11 9 39 23 33 25 36 81 290
2022/20232.033 199 196 16 147 177 214 1 102 908 11 43 19
2023/2024476 42 117 21 35 59 123 16 39 7 17 0 0
Totale 6.460